FinFET Based Designs: Power Analysis Considerations

The use of FinFET not only introduces additional challenges but also increases existing ones, especially with power budgeting, voltage drop, EM and overall power noise reliability sign-off.

More >

Power, Noise and Reliability Webinar Series On Demand

Presented by Apache customers and power experts

More >

An Efficient Approach to Evaluate Dynamic and Static voltage-drop on a Multi-Million Transistor SoC Design

Set-Top-Box SoC wire-bond and its adaptation for a flipchip: testcase and results -  describes key implementation approaches using Ansys’ RedHawk tool

More >

RTL Design-for-Power for Mobile SoCs: Best Practices - Educast

Learn Register Transfer Language (RTL) best practices for low-power mobile semiconductor design

Register >

SoC Power Integrity Challenges - Educast

ICs must deliver increased performance and functionality  while simultaneously lowering power budgets

More >