Apache at DAC 2010: Power and Noise Solutions for Chip-Package-System Convergence

Leading semiconductor companies present real user experience for RTL power reduction, power and reliability sign-off, and chip-package co-design

SAN JOSE, California – June 8, 2010 – Apache Design Solutions, the technology leader in power integrity and noise closure for chip-package-systems (CPS) convergence, will feature presentations by leading semiconductor companies including LSI, MoSys, STMicroelectronics, Texas Instruments, and TSMC, in Booth #535 at the 47th Design Automation Conference (DAC). The conference will take place at the Anaheim Convention Center, Anaheim, CA, from June 14th to June 16th, 2010. Apache will exhibit their PowerArtist™, RedHawk™, Totem, and Sentinel platforms for power integrity and noise closure from RTL to silicon, analog to digital, and chip to package and system flows. Apache will also showcase their recently announced PathFinder electro-static discharge (ESD) integrity solution for addressing the growing reliability challenges of ESD induced issues. For information on customer presentations, product demonstrations, and tutorials, and to register for any of the sessions,  please see http://www.apache-da.com/company/events/394

Additional Apache Design Solutions activities at DAC include:

Technical Panel

Wednesday, June 16th, from 9:00 until 11:00 am
Room 207AB
3D Stacked Die: Now or Future?

Moderator:
    Andrew Yang, Apache Design Solutions

Panelists:
    Pol Marchal, IMEC
    Riko Radojcic, Qualcomm
    Myung-Soo Jang, Samsung
    Philippe Magarshack, STMicroelectronics
    LC Lu, TSMC

User Track
Tuesday, June 15th from 1:30 until 3:00 pm
2nd Floor Foyer, Adjacent to Room 208AB

• Analysis of Power Delivery Network of Multiple Stacked ASICs using TSV and Micro-Bumps
• ESD Verification and ESD Aware Design Optimization for Complex System-on-Chip Design

Thursday, June 17th from 9:00 until 11:00 am
Room 208AB

• Package/PCB Aware On-Die Power Grid Noise Analysis
• Power Delivery Network Design and Analysis
• Power Noise Mitigation Strategy from RTL Perspective on MTCMOS Design
• An Accurate and Efficient SSO/SSN Simulation Methodology for 45nm LPDDR I/O Interface 

Exhibitor Forum

Booth #1562

• Chip-Package-System (CPS) Co-design/Co-analysis using Chip Power Model (CPM) by Bhavana Thudi, Apache Design Solutions, on Tuesday, June 15th from 3:15 until 3:50pm
• Reliability Verification for the Post 45nm Era by Arvind Shanmugavel, Apache Design Solutions, on Tuesday, June 15th from 3:55 until 4:30pm
• RTL Design for Power using PowerArtist-XP by William Ruby, Apache Design Solutions, on Wednesday, June 17th from 1:00 until 1:35pm