Resources

Whitepapers

Access to the following list of whitepapers require an Apache account. If you already have an account, please login. If you wish to request a new account, click on the Whitepaper you are interested in and you will be taken to the account registration page. Please allow 24 hours for access to Apache resources.

• Electronic Power and Thermal Management
  This paper presents a comprehensive set of tools and methodologies that can contribute to addressing the challenges of thermal and power management encountered in next-generation unmanned systems

• Excel2IR Early Design Analyssis Power Grid Prototyping Utility
  This white paper presents an analysis flow methodology enabling designers with early-stage high level design closure, with consideration for major power grid parameter checks, such as pads and power gates required number and location, power grid metal density used vs. reliability and IR drop targets, and more.

• Power Delivery Network (PDN) Verification Coverage
  This white paper presents a verification flow for high power grid verification coverage, with little effort, while identifying weak points early in the design cycle.

• RTL Design-for-Power Methodology
  This white paper presents a design-for-power methodology, beginning early in the design process at the Register Transfer Level (RTL) for maximum impact on power.

• Power and Noise Integrity for Analog/Mixed-Signal Designs
  This paper describes the need for power noise integrity solution for analog / mixed-signal designs and the benefits of the Totem platform, its usage model in a design flow, and results from simulation and correlation measurements.

• Power and Signal Line Electromigration Design and Reliability Validation Challenges
  This paper describes EM integrity analysis for power and signal lines. It outlines the various process and design trends that are increasing the likelihood of EM induced failures in a design and looks at conventional verification techniques for EM integrity and contrasts those with what is required for advanced process nodes.

• PathFinder™: Solution for Full-chip IC ESD Integrity
  This paper describes how PathFinder helps designers meet ESD guidelines and identify “weak” areas of the design (layout or circuit) most vulnerable to ESD failures. It also demonstrates how PathFinder can be used for early prototyping and design exploration, especially when clamp cells are inserted inside the core region of the chip.

• Advanced Modeling Technologies for Chip, Package, System Co-analysis and Co-optimization
  The traditional approach to chip-package-system (CPS) co-analysis and co-optimization lacks required accuracy and limits productivity. To meet the increasing demands for system cost down calls for a new methodology that is more comprehensive. This white paper outlines the Chip Power Model (CPM™) technologies and solutions available from Apache Design Solutions to help address the CPS convergence challenge.

• Technologies for Power, Signal, Thermal, and EMI Sign-off
  This whitepaper discusses the challenges associated with designing smaller, faster, and lower cost products and the necessity for an analysis methodology that addresses the cross domain effect in today's advanced process designs. The paper also provides an overview of Apache's power and noise solutions and how these products enable comprehensive chip-package-system convergence flow across multiple design disciplines.

• Power Noise Analysis for Next Generation ICs
  This paper describes the challenges associated with power delivery network designs and how RedHawk, a full-chip dynamic power analysis tool helps designers address the design failures caused by dynamic power noise.

• Low Power Design Analysis
  This paper describes the technology and methodology for analysis of designs utilizing power-gating switches for leakage control. It describes the requirements of verifying low power designs in different modes of operation, as well as in mixture of various states.

• Power Closure Flow
  This paper describes a power aware physical design methodology that includes power supply planning, resource allocation, and design (package, decap, and power grid network) in conjunction with sign-off quality verification to achieve faster design closures.

• Jitter & Critical Path Timing
  This paper describes the technology behind Apache's PsiWinder, which delivers standard-cell capacity and ease-of-use with Spice-accurate simulation of critical timing paths and clock tree network, including effects such as crosstalk and dynamic voltage drop.